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    > 產品資訊 > USB Hub Products > Hub Controller
    GL852F
    產品簡述

    GL852F is Genesys Logic’s USB general purpose compound solution which fully complies with Universal Serial Bus Specification Revision 2.0. It features 4 downstream ports and has one more internal downstream port connected to general purpose device. GL852F provides up to 17 General Purpose I/O (GPIO) pins to support general purpose and other applications. The MTT architecture provides every downstream port with individual traffic control for the best performance when connected with several Full/Low-Speed devices and running heavy bandwidth-consuming operations concurrently.


    GL852F embeds an 8-bit 8052-like microcontroller with 16 K-bytes built-in SRAM for firmware customization features.  The internal SRAM memory space supports multiple programming of applications firmware through USB upstream port, providing higher design flexibility comparing to traditional mask-ROM architecture.


    GL852F’s design architecture provides multiple advantages on minimizing the cost of system Built-of-Material (BOM).  For example, the hardware featured built-in 5 to 3.3V power regulator, on-chip power on reset, and internal Phase Lock Loop (PLL) that provide multiple clock sources with single 12MHz external crystal. In addition, OEM vendor’s configuration setting and PID/VID can be customized and stored in the internal memory to eliminate the need of using external EEPROM.


    *TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.


    General Features
    •    Compliant to USB specification 2.0
    •    On-chip 8-bit micro-processor
       –    Operation speed: 12MHz clock input
       –    8052-like architecture
       –    USB optimized instruction set
       –    C compiler support
       –    16 K-Byte embedded SRAM for multiple firmware programming
       –    max frequency 30Mhz
       –    256 byte of RAM for basic operation
    •    Integrated ultra low power USB transceiver
    •    Support both individual and gang modes of power management for each downstream ports
    •    Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down
    •    Configurable compound-device support
    •    On-chip 3.3V output provided by integrated 5-to-3.3V power regulator
    •    On-chip Phase Clock Loop (PLL) providing multiple clock source with single 12 MHz clock input
    •    Improved output drivers with slew-rate control for EMI reduction
    •    Internal power-fail detection for ESD recovery (watch dog timer)
    •    64 pin (7x7mm) LQFP and 48 pin (7x7mm) LQFP lead-free, RoHS compliant package

    USB Hub Features
    •    On-chip power-on reset (POR) USB hub Features
       –     4 downstream ports that fully compliant to USB specification Revision 2.0
       –     Multiple Transaction Translator (MTT) architecture that enhance performance
       –    Upstream port supports both high speed (HS) and full speed (FS) traffic
       –     Downstream ports support HS, FS, and low speed(LS) traffic
       –     Support 1 device address for hub, 1 device address for general purpose
       ♦   1 control pipe(endpoint 0: 64-byte data payload) and 1 interrupt pipe(endpoint 1: 1-byte data payload)
       ♦    1 control pipe(endpoint 0: 64-byte data payload) and 3 interrupt pipe(endpoint 2: 64-byte data payload; endpoint 3, 4: 8-byte data payload)
       –     backward compatible to USB specification Revision 1.1

    USB General Purpose Device Features
    •    Conforms to USB HID Class Specification, Revision 1.1
    •    I/O ports
       –     Up to 17 pins for general purpose I/O pin (LQFP64 package)
       –     Remote wakeup capability
       –     up to 6 pins can remote wakeup
       –     Unused I/O pins can be configured as status LED (see Ch3 pin descriptions for detail)
     


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